1. Field of the Invention
The present invention relates to a static semiconductor memory device. More particularly, the present invention relates to a static semiconductor memory device comprising a plurality of static memory cells connected to a plurality of complementary bit line pairs and to a plurality of word lines, for collectively writing data into each of the memory cells.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional static semiconductor memory device.
Referring now to FIG. 1, description is made on a structure of the conventional static semiconductor memory device. In FIG. 1, a memory cell array 2 comprises a plurality of memory cells 1 which are arranged in a matrix. In FIG. 1, the respective memory cells are indicated by symbols MC(1, 1), . . . , MC(m, n). A bit line load circuit 3 is connected between one ends of complementary bit line pairs 20a and 20b and a power supply 10. The bit line load circuit 3 comprises MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) Q.sub.C1, Q.sub.C2, . . . , Q.sub.Cn and Q.sub.D1, Q.sub.D2, . . . , Q.sub.Dn. A transfer gate 4 is connected to the other ends of the bit lines pairs 20a and 20b. The transfer gate 4 comprises MOSFETs Q.sub.A1, Q.sub.A2, . . . , Q.sub.An and Q.sub.B1, Q.sub.B2, . . . , Q.sub.Bn. I/O lines 22a and 22b are connected between the transfer gate 4 and a sense amplifier and writing circuit 6, respectively. Buffers 11 and 12 are connected to the sense amplifier and writing circuit 6, so that data is outputted through the buffer 11 and data is inputted externally through the buffer 12. Word lines 21 are connected to a row decoder 5, which selects any of the word lines.
FIG. 2 is a timing chart showing a write cycle of the static semiconductor memory device having shown in FIG. 1, and FIG. 3 is also a timing chart for explaining a read cycle.
Referring now to FIGS. 1 to 3, description is made on write and read operation of the conventional static semiconductor memory device. In the write cycle shown in FIG. 2, an address signal is applied to the row decoder 5, so that any of the word lines 21 is set to an "H" level. In addition, the transfer gate 4 selects a particular one pair of bit lines 20a and 20b and connects the pair of bit lines 20a and 20b to the I/O lines 22a and 22b. Therefore, the memory cells are driven by the sense amplifier and writing circuit 6. When a read/write control signal is at an "L" level, data is written into the memory cells. The data to be written into the memory cell 1 is not fixed to "0" but determined by data inputted through the buffer. As a result, when the read/write control signal at the "L" level is applied to the sense amplifier and writing circuit 6, data "0" is written into a predetermined memory cell.
On the other hand, in the read cycle shown in FIG. 3, the pair of bit lines 20a and 20b are driven by the memory cells 1, so that the level of one of the pair of bit lines 20a and 20b is decreased, as compared with the others thereof. The level of the pair of bit lines 20a and 20b is transmitted from the selected transfer gate 4 to the sense amplifier and write circuit 6 through the I/O lines 22a and 22b. When the read/write control signal is at the "H" level, data is outputted.
Meanwhile, after the static semiconductor memory device is manufactured in a factory, it must be examined before shipment whether or not data "0" or "1" can be written into all of memory cells. In addition, a system employing the static semiconductor memory device having may include a system that all memory cells must be reset when a power supply is recovered after disconnection of the power supply. Furthermore, it may be desired by a user that all of memory cells are reset.
However, as described in the above described operation in the write cycle, memory cells must be sequentially addressed when data "0" or "1" is written into the memory cells. Assuming that a cycle for designating an address of a single memory cell and writing the data "0" or "1" into the memory cell is one cycle, m x n cycles are required to write the data "0" or "1" into all of n memory cells shown in FIG. 1. Assuming that one cycle requires at least 100 nsec in a 256K static RAM, for example, a time period of 256K (1K=1024).times.100 nsec.div.26.2 msec is required.